Noise Coupling in Integrated Circuits
A Practical Approach to Analysis, Modeling, and Suppression
By: Cosmin Iorga, Ph.D.
What readers will gain:
Learn the mechanisms of noise generation, propagation, and reception at the physical structure levels of devices, chips, packages, and printed circuit boards.
Identify the coverage and limitations of various noise coupling suppression techniques.
Understand why conventional guard rings and shields reduce the noise coupling but do not completely eliminate it. Learn how to design additional circuit level noise cancellation by going through the methodology and by analyzing two design examples.
Learn how to reduce the noise generation by properly designing the power distribution at the system, board, package, and chip levels.
Discover how the power distribution resonance may generate significant amount of noise, and learn how to reduce the impedance of resonance peaks.
Find out why some very accurate noise coupling simulation tools may generate totally inaccurate results in some applications.
Learn how to select and use efficient noise coupling modeling and simulation tools based on the specific noise coupling mechanisms in each particular chip-package-PCB co-design.
Hardcover: 286 pages
Book Size: 6 x 9 x 0.8 inches
Publisher: NoiseCoupling.com, (2008)
ISBN: 978-0615197562 (acid-free paper)
TK7874.75.I74.2008 (PCIP block)
About the Author:
Dr. Cosmin Iorga has earned his Ph.D. in Electrical Engineering from Stanford University. Cosmin has accumulated over 20 years of experience in high-speed analog and mixed-signal circuit design and troubleshooting at system, board, and integrated circuit levels, with emphasis on signal integrity, power integrity, and noise coupling reduction. Cosmin has filed more than 15 patents with 9 granted so far, covering innovative solutions in noise coupling reduction and signal integrity. Cosmin is the author of the book “Noise Coupling in Integrated Circuits: A Practical Approach to Analysis, Modeling, and Suppression”.
Chapter one discusses fundamental concepts governing noise coupling mechanisms. The discussion covers thin film and volume distributed resistance and resistive coupling, high frequency skin effect, self, mutual, and loop inductance analysis starting from the microscopic view of internal current flow, inductive coupling, capacitance of semiconductor junctions and parallel wires, and capacitive coupling.
Chapter two presents an overview of integrated circuits fabrication technology focusing on those elements critical to noise coupling and power integrity. Various chip fabrication technologies are discussed, packaging techniques, printed circuit board structures, and power distribution networks in chip/package/PCB co-designs. The purpose is to prepare readers for the material presented in the following chapters.
Chapter three focuses on understanding the physical mechanisms that govern the noise generation in integrated circuits. Substrate noise generation is analyzed for various devices specific to different fabrication technologies and process options. Power supply noise generation is analyzed starting from the transient switching current and focusing on the parasitic elements of the power distribution on the chip, package, and PCB.
Chapter four talks about noise propagation. Three major propagation paths are presented: propagation through chip substrate, through power distribution network, and through signal crosstalk. Each of these paths are analyzed thoroughly from the fundamental physical phenomena to the top macro level.
Chapter five discusses the mechanisms of noise reception by sensitive circuits. Various devices and fabrication technologies are analyzed focusing on multiple levels from the microscopic physical mechanisms all the way to the macroscopic view and model development. Emphasis is placed on building or improving analysis skills of the noise coupling phenomenon, so that readers can apply the knowledge and techniques learned here to existing and future devices and technologies.
Chapter six focuses on measuring the noise coupling in integrated circuits. It emphasizes that the measurement process should not interfere with circuits by either changing the noise propagation or inserting additional noise from its own circuits. Various techniques are presented, and advantages and disadvantages are discussed. A novel technique using differential sensors for power and substrate noise and an on-chip waveform digitizer is presented. Readers learn how to perform accurate measurements and how to avoid the contamination of results from crosstalk or ground bounce.
Chapter seven focuses on suppressing the noise coupling in integrated circuits. Advantages, disadvantages, and limitations of various techniques are presented with relation to the physical structures of devices and substrate. Emphasis is placed on suppression by properly designing the power distribution at the system, board, package, and chip levels. The analysis results suggest that the choice and efficiency of suppression techniques depend directly on the specific noise coupling mechanisms of each individual case. To overcome the limitations of traditional suppression techniques, additional circuit level compensation may be considered. This chapter presents two design examples of circuit level compensation techniques and the experimental results from test chip measurements. The detailed presentations of these two techniques show the development procedures and the experimental results. These development procedures can serve as models for the design of noise cancellation techniques in other applications.
Chapter eight focuses on modeling and simulating the noise coupling in integrated circuits. The selection choice and use of conventional methods and tools are discussed, highlighting the advantages and limitations specific to various stages of the design flow. The importance of being able to predict the noise coupling early in the architectural stages of the design is emphasized. Since most of the existing tools do not offer a practical approach to noise coupling simulation in early stages, this chapter presents a modeling technique based only on the information typically available in the architectural definition stages of projects. The model is constructed based on the physical structure of devices, technology parameters available in the design guide, and statistical data from typical practices or previous designs. An example showing the model construction and correlation with measurements on a test chip is presented.
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