Skip to main content

Chip Package PCB

Co - Design
Home
Contact Us
Member Login
Book
Software
UCLA Extension Courses
ChipQuakeTM Power Integrity Explorer
Learning Edition
 
Highlights:

 

ChipQuakeTM provides fast frequency domain simulations of power integrity and noise coupling in mixed signal integrated circuits, including the effects of package and printed circuit boards (PCBs).

ChipQuakeTM allows design engineers and system architects to visualize power integrity and noise coupling tradeoffs in chip/package/PCB co-designs.

Overview:
 
     The effects of noise coupling are often noticed after fabrication, during characterization, or even after shipment to customers. Because of this, a large effort has been made in recent years to develop modeling techniques that predict the noise coupling before fabrication. 
 
     The prediction accuracy depends on the level of detail in the circuit description, which is imprecise in early architectural stages of designs and gradually increases in complexity as projects advance through the design process. The modeling techniques based on the physical layout are more accurate than the modeling techniques using the schematic, or architectural definition.
     However, the dominant noise coupling issues are related to the floor plan, pins assignment, guard rings, and the overall power distribution. Problems found in these areas often require major changes if discovered right before tape-out or even before layout.
 
     Therefore, especially in large and complex integrated circuits, it is essential to learn how to analyze and identify potential noise coupling issues early in the architectural definition of the project. ChipQuakeTM Power Integrity Explorer helps engineers learn the technical and intuitive skills needed to address noise coupling issues in chip/package/PCB co-designs early in the design process.

ChipQuakeTM Can Be Used To:
 
Analyze the power integrity on the chip, package, and printed circuit board (PCB)
 
Analyze the noise coupling effects on the analog regions of mixed-signal integrated circuits.
 
Examine various floor-plan options, pin assignments, power grid sizes, and guard ring isolations.
 
Analyze the effects of various packaging options on noise coupling.
 
Explore decoupling capacitor types, values, and placement locations on the chip, package, and PCB.
 
Inputs:
 
ChipQuakeTM uses the information available in the design specifications, technology manual, package datasheet or specifications, and statistical data from typical design practices or previous designs.
 
Outputs:
 
ChipQuakeTM generates two- and three-dimensional color coded maps of the substrate and power supply noise. Mouse move probing displays the noise voltage function of X-Y coordinates. ChipQuakeTM generates also frequency sweep characteristics of power supply rails on the chip, package, and PCB, and noise coupling at any X-Y coordinate in the analog region.
 
Simulation Time:
 
ChipQuakeTM is a fast simulator. Most simulations take only a few minutes.

Accuracy:
 
The estimation accuracy is lower compared to that provided by post- and pre-layout extraction and simulation tools but good enough to analyze the major physical mechanisms that contribute to power integrity and noise coupling degradation in integrated circuits.

Screen Shots: